1. Field of the Invention
The present invention relates to a circuit for generating a clock required for the operation of a microcomputer and a microcomputer including the clock generation circuit.
2. Description of Related Art
FIG. 1 is a block diagram of the configuration of a conventional microcomputer mainly around a clock generation circuit therein. As is shown in FIG. 1, a microcomputer 33 includes a clock generation circuit 103. Each electrode of a ceramic oscillator 10 is connected to each one terminal of load capacitances 11a and 11b which are grounded at the other terminals. A node between the ceramic oscillator 10 and the load capacitance 11a is connected to one input terminal of a NAND circuit 1. An output terminal of the NAND circuit 1 is connected to a node between the ceramic oscillator 10 and the load capacitance 11b. A negative feedback resistance 12 is interposed between the output terminal of the NAND circuit 1 and the one input terminal of the NAND circuit 1.
The other input terminal of the NAND circuit i is connected to a Q output terminal of a control register 5 for starting/stopping the oscillation of the ceramic oscillator 10. An S input terminal of the control register 5 is connected to an output terminal of an OR circuit 4 for outputting either an interruption signal or a reset signal for the microcomputer 33. The reset signal received by the OR circuit 4 is obtained by inverting a signal RESET by an inverter 3. A D input terminal and a clock (CK) input terminal of the control register 5 are connected to a CPU 16 of the microcomputer 33. An output terminal of the inverter 3 is also connected to the CPU 16.
An oscillation voltage generated by the ceramic oscillator 10 at the output terminal of the NAND circuit 1 is buffered by an inverter 2 to be shaped into a pulse, which is supplied to a counter 24. The pulse shaped by the inverter 2 is also supplied to one input terminal of an AND circuit 6. An overflow output Q of the counter 24 is supplied to an S input terminal of an R-S flip-flop 25. A Q output of the R-S flip-flop 25 is supplied to the other input terminal of the AND circuit 6.
A Q output terminal of the control register 5 is connected to one input terminal of an OR circuit 7 with the other input terminal being connected to the output terminal of the inverter 3. An output terminal of the OR circuit 7 is connected to R input terminals of the counter 24 and the R-S flip-flop 25.
A clock output by the AND circuit 6 is supplied to the CPU 16, an acceleration-purpose input/output circuit 27 for the CPU 16 and peripheral circuits of the microcomputer 33 such as a timer circuit 28. The CPU 16 is connected to a high speed arithmetic circuit 26 for speeding up processing by the CPU 16.
Now, the operation for starting the oscillation of the ceramic oscillator 10 will be described.
It is when power is applied to the microcomputer 33 and when an external interruption signal is input in a clock halt mode that the oscillation of the ceramic oscillator 10 starts. In the clock halt mode, "L" is written in the control register 5 in response to a signal output by the CPU 16 so as to allow the Q output of the control register 5 to undergo a high-to-low transition, thereby stopping the oscillation of the ceramic oscillator 10. When an interruption signal is input from outside in the clock halt mode, the control register 5 is set to allow the Q output of the control register 5 to undergo a low-to-high transition. Herein, the case where the oscillation starts from the clock halt mode by an external interruption signal will be described referring to a diagram of waveforms of the respective outputs shown in FIG. 2.
When the OR circuit 4 receives an interruption signal, the output of the OR circuit 4 undergoes a low-to-high transition, thereby setting the control register 5 to allow the Q output to undergo a low-to-high transition. As a result, the ceramic oscillator 10 starts oscillating from the high level as is shown with a broken line in FIG. 2.
At the initial stage of the oscillation of the ceramic oscillator 10, an oscillation voltage has a small amplitude and exhibits an unstable waveform including higher order frequencies (by approximately three to four times). The unstable waveform is shaped by the inverter 2 as shown in FIG. 2. When the thus shaped waveform is directly used as a clock, the frequency is so high that an operation speed of an element cannot follow the clock cycle. This results in malfunction and run away of the microcomputer 33 and hinders the normal operation of the microcomputer 33.
Accordingly, in the conventional microcomputer, a clock is not output until the ceramic oscillator 10 attains stable oscillation. Specifically, the counter 24 counts up pulses shaped by the inverter 2 for a period of time required for the ceramic oscillator 10 to attain the stable oscillation, and the R-S flip-flop 25 is set in response to the overflow signal Q of the counter 24. At this point, the Q output of the R-S flip-flop 25 undergoes a low-to-high transition, thereby allowing a pulse shaped by the inverter 2 to be output as a clock from the AND circuit 6.
The counter 24 and the R-S flip-flop 25 are reset in the clock halt mode when the Q output of the control register 5 undergoes a high-to-low transition and the Q output thereof undergoes a low-to-high transition. In addition, when power is applied to the microcomputer 33, the counter 24 and the R-S flip-flop 25 are reset through the input of a signal RESET (at a low level; hereinafter abbreviated to "L" ) to the inverter 3 and the output (at a high level; hereinafter abbreviated to "H") from the inverter 3.
The ceramic oscillator 10, however, requires several tens .mu.sec. (a quartz oscillator requires several msec. to 30 msec.) to attain the stable oscillation from the start of the oscillation. This time period is sufficiently long enough for the microcomputer to conduct several tens steps of an operation. Therefore, especially in a portable information equipment or the like that reduces power consumption by stopping a clock while the operation of a microcomputer is not necessary, this time period cannot be used for a returning operation since a clock is not output until the oscillation stabilizes, thereby delaying the returning operation by the microcomputer.